1. Field of the Invention
The invention relates to a test circuit for large scale integrated circuits on a wafer, and more particularly to a test circuit for large scale integrated circuits on a wafer for an improvement in a testability thereof.
2. Description of the Related Art.
The importance of the testability of the large scale integrated circuits on a wafer is on the increase as scaling up of the integrated circuits. Further, improvements in both an efficiency of a wafer test for the large scale integrated circuits and an area usage factor of the wafer are also required for improvements in a high density of the wafer and scaling up of the integrated circuit.
A conventional layout of large scale integrated circuits will be described with reference to FIG. 1. A wafer 10 includes a plurality of pellets or die regions in which large scale integrated circuits (LSI circuits) 20 are provided. The pellets are isolated by scribe lines or dicing lines 100, each of which has a width of approximately 100 micrometers. In the prior art, the wafer test of the every LSI circuits 20 are sequentially conducted by use of an external tester or the like. Since the LSI circuits 20 are electrically separated from each other through the dicing lines 100, the wafer test of the individual LSI circuits 20 is carried out sequentially and independently. The sequential wafer test for every the LSIs 20 results in a low efficiency of the wafer test and in an inferior of the area usage factor of the wafer. This causes a difficulty of the improvement in the testability of the large scale integrated circuits. Accordingly, it is urgently needed to settle the above problems with the testability of the LSI circuits on the wafer.
In the prior art, a simultaneous test of a plurality of the LSI circuits 20, however, requires much time and a large expense which are not practical.
When LSI circuits possess a high speed performance, a performance speed of the tester seems no longer responsive to the high speed performance of the LSI circuits. The test of the LSI circuits on the wafer is carried out by contacting a probe of a tester head with input/output pads of the LSI circuits. This causes a problem with a relatively large contact resistance between the probe of the tester head and the pad of the LSI circuits. Such large contact resistance makes it much more difficult to conduct a high speed test of the LSI circuits.
To settle the problem with the large contact resistance, a built-in self test method has been proposed. In this method, in replacement of the external tester a test circuit is provided on the wafer together with the LSI circuits. The built-in self test method has, however, the following problem. Each of the LSI circuits requires a test circuit, namely, the same number of the test circuits as the number of the LSI circuits are required. This is unsuitable in view of the area usage factor of the wafer and thus not preferable for improvement in the high density of the wafer and the scaling up of the integrated circuits.
In the prior arts, the Japanese laid-open patent application No. 62-171136 discloses another method in which test circuits and LSI circuits are provided on a single wafer but are electrically separate from each other so that any input pad to be contacted with the probe of the tester is separated from each of the LSI circuits as the final products. Such method also has the above problem. Each of the LSI circuits also requires a test circuit, namely the same number of the test circuits as the number of the LSI circuits are required. This is unsuitable in view of the area usage factor of the wafer and thus not preferable for improvement in the high density of the wafer and the scaling up of the integrated circuits.
Alternatively, the Japanese laid-open patent application No. 62-217625 discloses other method in which exclusive power supply lines for the test are provided to supply the power to every block of the LSI circuits on the wafer. The method also has the above problem. Namely, each of the plural LSI circuits requires a test circuit. The same number of the test circuits as the number of the LSI circuits are, therefore, required. This is unsuitable in view of the area usage factor of the wafer and thus not preferable for improvement in the high density of the wafer and the scaling up of the integrated circuits.
Yet another method is disclosed in the Japanese laid-open patent application No. 62-217625. Power supply lines for the test are provided on the scribe lines of the wafer to supply the power to a plurality of the LSI circuits on the wafer so as to conduct a simultaneous test of the plural LSI circuits. The method also has the above problem. Each of the plural LSI circuits requires a test circuit. Accordingly, the same number of the test circuits as the number of the LSI circuits are required. This is unsuitable in view of the area usage factor of the wafer and thus not preferable for improvement in the high density of the wafer and the scaling up of the integrated circuits.
It is, therefore, required to develop a novel test circuit for the LSI circuits which is able to settle the above problems.